Design, Layout and Realization of an All NOR Enhancement Type PMOS Serial Adder

A four bit serial adder was designed with PMOS NOR gates from a truth table that models binary serial addition. Three storaqe reqisters were also included in the desiqn, two-four bit shift registers for the incoming digits and one-five bit register for the sum. A simple five gate latch was used for the bits of these registers. The cir­cuit was layed out using ICE , a software program designed to facilitate circuit layout for mask making at R.I.T