Design and simulation of a primitive RISC architecture using VHDL

Hardware Description Languages are used as the connecting links between the design of a digital system and the way this design is being represented in computers, with the ultimate goal being the simulation and verification of that design before the construction of any prototype. In this thesis, we follow all the steps of a RISC architecture design and finally use VHDL as the tool to describe, simulate and verify the design. By the unique abilities of VHDL we give both a structural and a behavioral description where the latter contains multiple description levels, from gate to Processor-Memory-Switch (PMS) . The final step is the simulation to verify the proper operation of the design or to assist in pinpointing design errors for correction