Simulation of a morphological image processor using VHDL - Part I: Mathematical Components

Very high speed integrated circuit Hardware Description Language (VHDL) is utilized in this project to model a Morphological Image Processor (MIP) Array. Both behavioral and structural models have been established at the system level, and the simulation results from both models are consistent with each other. The successful implementation of the models accomplishes our original goal to document the MIP with VHDL. It is observed from the project that VHDL is a powerful language. It is flexible since it can be used to model any level of a system independent of the technology