Gaussian filtering is a basic tool for image processing. Noise reduction, scale-space generation or edge detection are examples of tasks where different Gaussian filters can be successfully utilized. However, their implementation in a conventional digital processor by applying a convolution kernel throughout the image is quite inefficient. Not only the value of every single pixel is taken into consideration sucessively, but also contributions from their neighbors need to be taken into account. Processing of the frame is serialized and memory access is intensive and recurrent. The result is a low operation speed or, alternatively, a high power consumption. This inefficiency is specially remarkable for filters with large variance, as the kern...
This paper addresses the design and VLSI implementation of MOS-based RC networks capable of performi...
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian p...
This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an...
Incorporating multi-resolution capabilities into imagers renders additional power saving mechanisms ...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO pr...
Aiming at designing a CMOS image sensor that combines high fill factor and focal-plane implementati...
Abstract—Incorporating multi-resolution capabilities into im-agers renders additional power saving m...
Stand-alone applications of vision are severely constrained by their limited power budget. This is o...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO ...
Early vision stages represent a considerably heavy computational load. A huge amount of data needs t...
This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CM...
Focal-plane Sensor-Processor Arrays (FPSPs) are new imaging devices with parallel Single Instruction...
This paper addresses a comparison of architectures for the hardware implementation of Gaussian image...
This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26...
Portable applications of artificial vision are limited by the fact that conventional processing sche...
This paper addresses the design and VLSI implementation of MOS-based RC networks capable of performi...
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian p...
This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an...
Incorporating multi-resolution capabilities into imagers renders additional power saving mechanisms ...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO pr...
Aiming at designing a CMOS image sensor that combines high fill factor and focal-plane implementati...
Abstract—Incorporating multi-resolution capabilities into im-agers renders additional power saving m...
Stand-alone applications of vision are severely constrained by their limited power budget. This is o...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO ...
Early vision stages represent a considerably heavy computational load. A huge amount of data needs t...
This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CM...
Focal-plane Sensor-Processor Arrays (FPSPs) are new imaging devices with parallel Single Instruction...
This paper addresses a comparison of architectures for the hardware implementation of Gaussian image...
This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26...
Portable applications of artificial vision are limited by the fact that conventional processing sche...
This paper addresses the design and VLSI implementation of MOS-based RC networks capable of performi...
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian p...
This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an...