A high-performance Sigma-Delta modulator for wireline communication applications is presenfed It employs a 4th-order cascade multi-bit architecfure that requires only 16 oversampling ratio, and has been implemented using fully-differential SC circuits in a 0.25-μm CMOS technology. Measurements show a dynamic range of 84dB operating at 2.2MS/s output rate, and 79dB at 4.4MS/s. The whole prototype dissipates 65.8mW from a 2.5-V supply.European Commission UM1-34283mAMES-2Ministerio de Ciencia y Tecnología TIC2001-0929/ADAVER
Graduation date: 2015Access restricted to the OSU Community, at author's request, from Sept. 4, 2014...
There is an increasing demand for low-power, high-signal-band-width SoCs. The challenges faced by de...
A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor a...
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at ...
Graduation date: 2011As CMOS processes keep scaling down devices, the maximum operating frequencies ...
In this paper, two high-resolution mediumbandwidth single-loop 4 th-order single-bit sigma-delta mod...
This paper presents a sixth-order sigma-delta modulator capable of 16 bit resolution with an oversam...
A double-sampling sigma delta-ADC with bilinear integrators and a 7-level quantizer is presented. It...
An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of ...
A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor a...
As CMOS technology shrinks, the transistor speed K-quantizing paths and can achieve significantly hi...
This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma (∆Σ)...
The design of single loop two-order Delta-Sigma modulator with feed forward structure is presented i...
[[abstract]]This work presents a wideband cascaded sigma-delta modulator (CLFSDM) that reduces the n...
This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modu...
Graduation date: 2015Access restricted to the OSU Community, at author's request, from Sept. 4, 2014...
There is an increasing demand for low-power, high-signal-band-width SoCs. The challenges faced by de...
A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor a...
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at ...
Graduation date: 2011As CMOS processes keep scaling down devices, the maximum operating frequencies ...
In this paper, two high-resolution mediumbandwidth single-loop 4 th-order single-bit sigma-delta mod...
This paper presents a sixth-order sigma-delta modulator capable of 16 bit resolution with an oversam...
A double-sampling sigma delta-ADC with bilinear integrators and a 7-level quantizer is presented. It...
An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of ...
A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor a...
As CMOS technology shrinks, the transistor speed K-quantizing paths and can achieve significantly hi...
This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma (∆Σ)...
The design of single loop two-order Delta-Sigma modulator with feed forward structure is presented i...
[[abstract]]This work presents a wideband cascaded sigma-delta modulator (CLFSDM) that reduces the n...
This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modu...
Graduation date: 2015Access restricted to the OSU Community, at author's request, from Sept. 4, 2014...
There is an increasing demand for low-power, high-signal-band-width SoCs. The challenges faced by de...
A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor a...
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