Efficient design of hardware-enabled reservoir computing in FPGAs

International audienceIn this work, we propose a new approach toward the efficient optimization and implementation of reservoir computing hardware, reducing the required domain-expert knowledge and optimization effort. First, we introduce a self-adapting reservoir input mask to the structure of the data via linear autoencoders. We, therefore, incorporate the advantages of dimensionality reduction and dimensionality expansion achieved by conventional algorithmically-efficient linear algebra procedures of principal component analysis. Second, we employ evolutionary-inspired genetic algorithm techniques resulting in a highly efficient optimization of reservoir dynamics with a dramatically reduced number of evaluations comparing to exhaustive search. We illustrate the method on the so-called single-node reservoir computing architecture, especially suitable for implementation in ultrahigh-speed hardware. The combination of both methods and the resulting reduction of time required for performance optimization of a hardware system establish a strategy toward machine learning hardware capable of self-adaption to optimally solve specific problems. We confirm the validity of those principles building reservoir computing hardware based on a field-programmable gate array