Layout automation for analog and mixed-signal integrated circuits

Recently, the demand for analog and mixed-signal (AMS) integrated circuits (ICs) has increased significantly due to various emerging applications. However, most of the AMS IC layout design efforts are still handled manually at present, which is time-consuming and error-prone. The AMS layout automation level is far from meeting the need for fast layout-circuit performance iterations to accommodate the rapid growth of the market. In general, the methodologies adopted by AMS layout automation tools mainly fall in several different categories: (1) optimization-based approach, which is the most widely used one; (2) template-based approach (e.g., for layout retargeting); and (3) standard cell-based digitalized AMS circuit design and synthesis methodology, which is a new direction preferable in advanced process technology nodes. This dissertation proposes a set of techniques and algorithms to address various practical problems in these major directions of analog and mixed-signal circuit layout automation research. For the direction of the optimization-based AMS IC layout automation, two analog placement algorithms are proposed to improve the layout results from different aspects. Firstly, hierarchical placement techniques for highperformance AMS ICs are proposed, which minimize the critical parasitics in addition to the total area and half-perimeter wirelength, while satisfying the analog placement constraints simultaneously, including symmetry and proximity group constraints. Secondly, an analytical framework is proposed to tackle the device layer-aware analog placement problem, which can effectively reduce the total area and wirelength without degrading the circuit performance, leveraging the fact that it can be beneficial to overlap some devices built by mutually exclusive layers. For the direction of the template-based approach, this dissertation also proposes a new layout retargeting framework. It first applies effective algorithms to extract analog placement constraints from previous quality-approved layouts, including symmetry and regularity constraints. After that, it preserves the prior design expertise during retargeting while exploring different layout topologies to improve the result quality. Furthermore, for both optimization-based and template-based AMS IC layout automation approaches, well island generation persists as a fundamental and unresolved challenge in the post-placement optimization stage. To address the well generation problem, this dissertation proposes a generative adversarial network (GAN) guided framework with a post-refinement stage to mimic the behavior of experienced designers in well generation, leveraging the previous high-quality manually-crafted layouts. Guiding regions for the well islands are first generated by a trained GAN model, after which the results are legalized through post-refinement to satisfy the design rules. Finally, for the standard cell-based digitalized AMS IC design and synthesis methodology, this dissertation presents a scaling compatible, synthesis friendly ring voltage-controlled oscillator (VCO) based ∆Σ analog-to-digital converter (ADC). Its circuit performance improves as process technology advances, and its layout can be fully synthesized by leveraging digital circuit automation tools. It also demonstrates favorable performance compared with the prior digitalized ADCs and in-line performance with state-of-the-art manual designs.Electrical and Computer Engineerin