Energy Efficient Mixed Signal Circuit Techniques for Machine Learning and Security Applications

The recent aggressive scaling of CMOS technology for increased performance, higher component density, and reduced cost-per-gate has significantly benefited digital systems. The increase in speed and the increase in density of these systems have enabled the performance and efficiency required for hardware implementations of meaningful machine-learning and neural-network systems. Most machine-learning hardware implementations from the past decade are digital. However, many machine-learning systems require only low accuracy and therefore do not need the inherent accuracy of digital processing. Instead, analog or mixed-signal circuitry may enable far more efficient neural network implementations. Internet of Things (IoT) edge-computing typically requires digital pre-processing or machine learning feature extraction of data from sensor nodes. This digital processing can consume a significant amount of energy in energy-constrained sensor nodes. Pre-processing and feature extraction in the analog domain can be much more efficient. Potentially this can also entirely remove the need for a DSP core saving even more power and die-area. An additional challenge is that while the increased capability of CMOS circuits has enabled single-chip systems, the responsibility for both critical decision making and processing sensitive information is now concentrated in a single device. The rush to capitalize on advanced CMOS technologies has often involved little or no consideration on securing these single-chip systems, resulting in a potential for dangerous security exploits. Our work tackles the energy efficiency and security of IoT and edge devices with new mixed-signal techniques for machine-learning and security. First, we address the inefficiency of low-resolution machine learning processing by creating a hybrid analog-digital computational node that is compatible with an all-digital CAD flow. This 512 hybrid-neuron neural network achieves a 2x efficiency improvement over a comparable digital design while maintaining reliable classification results over PVT. Second, we address IoT edge computing with an analog machine-learning interface that performs linear analog computation during the analog-to-digital digitization process. A prototype increases inner-product multiplicand resolution by 2x (from 8 to 16 bits) over the state-of-the-art. Third, we present a mixed-signal true random number generator that uses both digital and analog noise-shaping to generate a truly random bitstream (as determined by NIST SP 800-22r1). The energy efficiency is 3nJ/bit which includes the analog entropy source, resulting in best-in-class performance. Fourth, addressing the security of the sensor interface, we introduce the first side-channel attack immune digitizer with embedded information barriers that prevent sensitive information from being generated.PhDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/151480/1/fbuhler_1.pd