Pulsed High Current Characterization of Highly Integrated Circuits and System

The Charged Device Model ( CDM ) describes the primary cause for Electrostatic Discharge (ESD) failures in manufacturing and automatic handling. The CDM test method is the standardized procedure used worldwide to characterize the susceptibility of a device to damage from ESD under CDM conditions. Prevailing trends in the semiconductor industry like technology scaling towards the deep sub-10-nm regime or the steady increase in data rates in high-speed IOs (> 50Gbps) have come at the expense of degraded ESD robustness, entailing new challenges in the field of ESD protection as well as in ESD testing. The resulting demand for improved CDM test precision steadily reveals the limitations of the CDM testing method, which is highly unreliable due to the air discharge. Because of the very poor repeatability of CDM testing, a contact-mode ESD test method called Capacitively Coupled Transmission-Line Pulsing (CC-TLP) was developed, starting two decades ago by Gieser and Wolf, when the risk of false CDM test results was still limited. This thesis mainly deals with the question if CC-TLP is capable to complement or even replace the commonly used CDM testing method for product development and characterization of challenging package setups and very advanced high-speed technologies today and beyond. Like todays CDM testing, CC-TLP needs to reproduce exactly the failure locations and failure signatures of real world CDM events. Tested devices should fail at about the same peak stress current within the ±20% tolerance of the current CDM standard. This was already demonstrated in several correlation studies between CDM and CC-TLP on technologies up to 90nm CMOS in the last decades. In view of issues of CDM correlating voltage failure thresholds between compliant CDM testers in many cases, this thesis studies the intrinsic stress factors relating the two test methods. It investigates in detail both test methods and their correlation on following, very advanced technologies, motivated by the fact that there was no simple correlation between the peak currents obtained. A) A large Chip-on-Flex (COF) assembly with a highly chargeable foil substrate B) A very small packaged Integrated Circuit (IC) designed in a 0.25µm BCD technology C) A 28nm CMOS IC for network applications with ultra-high-speed (25Gbps) interface Challenging the limits of todays metrology and test setups , a characterization and significant improvement of the impulse setup enabled an accurate generation, controlling and monitoring of intrinsic stress parameters like the CC-TLP current rise time or slew rate. In order to reach a current rise time resolution in the single-digit ps-domain, post measurement embedding/de-embedding techniques were implemented. These were essential prerequisites for an exhaustive comparison of both test methods and revealed that the energy content of the pulses and cumulative stress effects (A) as well as the stress current slew rate (B,C) can have a direct influence on the failure threshold. Despite decades of application, there is still a significant lack of understanding about the influences of critical stress parameters beyond the peak current as well as the interaction of the tester and the Device under Test (DUT) including the package, particularly because the investigation of these parameters is not directly addressable by the poorly reproducible CDM test method. Thanks to the single-digit ps-resolution and precision of the highly reproducible CC-TLP test method, which additionally provides wafer-level capabilities and the possibility to control key parameters like the rise time or the pulse width of the stress, this thesis is one of the first to directly analyze the influence of critical stress factors on advanced semiconductor technologies at device and wafer level. Furthermore, this thesis contains not only CC-TLP investigations of CDM typical gate oxide ruptures but, for the first time, a pn-junction failure (A). The thesis also presents an innovative method for scanning the surface potential across e.g. PCB s or flexible electronics (A), providing specific information for identifying root causes of the electrostatic stress. Circuit simulations support the experiments and provide a deep insight into the general correlation between CDM and CC-TLP with respect to the variation of specific test parameters. The outcome of this work is pushing forward the frontiers of todays ESD testing in the CDM domain and is expected to play a decisive role for future standardization of CDM and alternative stress test methods like CC-TLP