Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era

The Daughterboard (DB) is the read-out link and control board that interfaces the on- and off-detector electronics for the High-Luminosity Large Hadron Collider (HL LHC) of the the ATLAS Tile Calorimeter (TileCal). The DB sends high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC timing. A redundant design, Xilinx Soft Error Mitigation (SEM), Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC Cyclic Redundancy Check (CRC) strategies minimize single failure points while withstanding single-event upsets and damage from minimum ionizing and hadronic radiation. We present the current results of the performed TID, NIEL and SEU tests, aiming to demonstrate the readiness of the Daughterboard to satisfy the radiation requirements imposed by the HL LHC