AHRC: An Optimized Cache Associativity

© 2016 IEEE. Hardware resources require efficient scaling because the future of computing technology seems to be intensive multithreaded. One of the main challenges in the scalability of computers hardware is the hierarchy of the memory. Chip-multiprocessors (CMPs) rely on large and multi-level hierarchies of caches to reduce cost of resources and improve systems performance. These multi-level hierarchies are the ones, which also help to solve the issue of limited bandwidth and minimize the latency of the main memory. Almost half of the area of the chip and a large percentage of the system energy is used by caches. One of the main problems limiting the scalability of cache hierarchies is called cache associativity. Caches consume a lot of energy to implement associative lookups. This affects the performance of the system by reducing the efficiency of caches. This paper describes a new design of cache that we called - Adaptive Hashing and Replacement Cache (AHRC). This design has the ability of maintaining high associativity with an advanced method of replacement policy. AHRC can improve associativity and maintain the number of possible locations, where each block is kept as small as possible. Several workloads were simulated on a large-scale CMP with AHRC as the last-level cache. We propose an Adaptive Reuse Interval Prediction (ARIP) scheme for AHRC, which is superior to the NRU scheme that was described by Seznec. Results demonstrate that AHRC has better energy efficiency and higher performance as compared to conventional caches. Additionally, large caches that utilize AHRC are the most suitable in many core CMPs to provide a more significant improvement and scalability than the smaller caches. However, AHRC with a higher-level replacement may lead to loss of energy for workloads that are not sensitive to the policy governing the replacement process