FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

ABSTRACT Hardware implementation of proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on an FPGA (field programmable gate array) as well as a PC (running LabVIEW) for multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using National Instruments (NI) Universal Software Radio Peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. Results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of proposed algorithms on a Xilinx Virtex-5 FPGA using LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for real-time practical applications. Moreover, performance comparison with QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of estimation accuracy, computation speed, and FPGA resources consumed