Present day multi-core processors integrate dozens of small processing cores with an on-chip network consisting of point-to-point links. The network enables communication between the processing cores and sharing of common resources such as memory and I/O controllers. In this work, we propose an arbitration scheme to ensure fair-deal service in accessing a chips shared resources by eliminating any bias in accessing a shared resource by a core based on its location in the multi-core chip. We propose using probabilistic arbitration combined with distance-based weights to achieve fair-deal service and overcome the limitation of conventional round-robin arbiter. We describe how nonlinear weights need to be used with probabilistic arbiters and pr...
The advent of multicore processors complicates timing analysis owing to the need to account for the ...
The multi-processor cores in SoC which have high burst data transactions can play a critical role wh...
This paper proposes an architecture of a virtual channel router for an on-chip network1. The router ...
Many-core processors will have many processing cores with a network-on-chip (NoC) that provides acce...
In Proc. of the 2014 Makassar International Conference on Electrical Engineering and Informatics (MI...
Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case ...
Arbiter is the core element in shared-resources systems such as in network-on-chip (NoC), convention...
All arbiters proposed in the literature suffer from one of the following problems: large time comple...
NUMA (non-uniform memory access) servers are commonly used in high-performance computing and datacen...
Large scale chip multiprocessors employ a multi-NoC, consisting of multiple physical channels for in...
Interconnection networks consist of a set of switches in-terconnected by point-to-point links, and h...
Switch design for interconnection networks plays an important role in the overall performance of mul...
This paper describes the efficient arbitration scheme of an interface that provides access by ...
Abstract—In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing ele...
In a multicore processor, arbitrating the shared resources so as to ensure predictable latencies for...
The advent of multicore processors complicates timing analysis owing to the need to account for the ...
The multi-processor cores in SoC which have high burst data transactions can play a critical role wh...
This paper proposes an architecture of a virtual channel router for an on-chip network1. The router ...
Many-core processors will have many processing cores with a network-on-chip (NoC) that provides acce...
In Proc. of the 2014 Makassar International Conference on Electrical Engineering and Informatics (MI...
Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case ...
Arbiter is the core element in shared-resources systems such as in network-on-chip (NoC), convention...
All arbiters proposed in the literature suffer from one of the following problems: large time comple...
NUMA (non-uniform memory access) servers are commonly used in high-performance computing and datacen...
Large scale chip multiprocessors employ a multi-NoC, consisting of multiple physical channels for in...
Interconnection networks consist of a set of switches in-terconnected by point-to-point links, and h...
Switch design for interconnection networks plays an important role in the overall performance of mul...
This paper describes the efficient arbitration scheme of an interface that provides access by ...
Abstract—In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing ele...
In a multicore processor, arbitrating the shared resources so as to ensure predictable latencies for...
The advent of multicore processors complicates timing analysis owing to the need to account for the ...
The multi-processor cores in SoC which have high burst data transactions can play a critical role wh...
This paper proposes an architecture of a virtual channel router for an on-chip network1. The router ...