Novel high precision current mode multiplier/divider circuit based on the translinear principle

Her geçen gün kullandığımız elektronik cihazların daha da küçülmekte olduğu, daha küçük ve çok fonksiyonlu elektronik cihazlara olan ihtiyacın artarak devam ettiği göz önüne alındığında, devre tasarımcılarının devreyi oluşturan MOS tranzistorlardaki ikincil etkileri daha çok dikkate alması gerekliliği ortaya çıkmaktadır. Buradan hareketle gerçekleştirilen bu çalışmada, karesel işlemlerde kullanılan MOS translineer devrelerinin çıkış akım fonksiyonlarındaki küçülen boyutlar nedeniyle oluşan hatanın azaltılmasına yönelik önerilen yöntemle, karekök alıcı ve kare/bölücü devreler tasarlanmıştır. Tasarlanan bu devrelerin birlikte kullanılmasıyla yeni bir çarpıcı/bölücü devre önerilmiştir. Önerilen bu devrenin çıkış akım fonksiyonu, aynı MOS tranzistor boyutlarıyla kurulan klasik yapının çıkış fonksiyonuyla ve ideal fonksiyon ile karşılaştırılmıştır. Önerilen devrenin yüksek doğruluklu olduğu ve devrenin avantajları sunulmuştur. Ayrıca önerilen çarpıcı/bölücü devreyi oluşturan karekök alıcı ve kare/bölücü devrelerin bir VC kontrol gerilimiyle ayarlanabilir olması, önerilen devrenin çıkış akım fonksiyonunun da elektronik olarak ayarlanabilir olmasını beraberinde getirir. Bunun yanında önerilen çarpıcı/bölücü devreyle yüksek doğrulukta çıkış akım fonksiyonu elde edilebilmenin yanı sıra bu devrede emsallerine göre daha küçük boyutlarda MOS tranzistor kullanımı mümkün olmaktadır. Böylece kırmık üzerinde çok daha az yere ihtiyaç olacak ve yüksek frekanslarda çalışmaya olanak yaratılmış olacaktır. Önerilen çarpıcı/bölücü devrenin uygulaması olarak bir frekans katlayıcı devre de gerçekleştirilmiş ve önerilen devrenin, klasik yapılarla kurulacak olan devreye göre çok daha yüksek doğrulukla çıkış akımı ürettiği gösterilmiştir. Tüm analizler SPICE benzetim programında gerçekleştirilmiştir. Anahtar Kelimeler: MOSFET ikinci dereceden etkilerin azaltılması, karekök alıcı devre, kare/bölücü devre, çarpıcı devre, frekans katlayıcı.Electronic devices we use in our daily life are getting smaller from day to day and the need for smaller and more functional devices is increasing. This leads researchers to reduce chip area and power consumption, to develop new design techniques and to use smaller devices on the circuits. It is well known that the decrease in dimensions of MOS transistor in IC fabrication technology affects MOS transistor performance and the MOS transistor voltage current relationship changes from square law to linear. Therefore errors may occur in the output current function of the current mode circuits employing small sized MOS transistors. Nowadays, due to the decrease in dimensions of MOS transistors in IC fabrication, second order effects cause more errors in the MOS transistor performance. Actually drain current expression includes effects of W, L and VDS on effective threshold, velocity saturation effects, effective mobility dependence on normal field and channel length modulation. Especially, the short channel effects become more important in MOS transistors at channel lengths of about 1 m or less and require modifications to the MOS models as well as the circuits that are designed using these MOS transistors. Due to the second order effects small sized MOS transistors do not operate properly and therefore errors may occur in the output current function of the current mode circuits employing these transistors. The multiplication of two current signals is one of the most important operations in analog signal processing. Recently several CMOS multipliers have been reported and some of them are based on MOS translinear principle. Translinear circuit principle which was originally formulated for loops of bipolar transistors is generalized and the MOS translinear loop (MTL) principle is derived by Seevinck in 1991. MTL circuits are designed by applying MTL principle and used in synthesizing many nonlinear signal processing functions such as square rooting. Square root and squarer/divider circuit are two important structures of the MTL circuits and a multiplier/ divider circuit can be obtained by using both square root and squarer/divider circuit. In this paper, a method is proposed to reduce the errors generated by the second order effects in the current mode circuits employing MOS translinear loop. This method is applied to the current mode the square root and squarer/divider circuit. Thus high precision square root circuit and high precision squarer/divider circuit are proposed. Furthermore multiplier/divider circuit which contains these proposed circuits is designed and presented. Proposed circuits have been simulated with SPICE simulator using 0.35 µm CMOS technology parameters. The small signal and DC transfer characteristics of the current functions of the proposed circuit and the conventional circuit are observed. The DC transfer characteristics of the output current function of the proposed multiplier/ divider circuit shows approximately the ideal current function and the output current function of the conventional circuit is very different from the ideal curve. The output current function of the proposed circuits can be controlled by a control voltage. The small signal bandwidth of the proposed multiplier/divider circuit is about 50 MHz. Analog building blocks such as analog modulator, frequency doubler and etc. can be easily obtained using the proposed multiplier/divider circuit. The frequency doubler circuits are used in microwave, radar and wireless communication circuits frequently. So a frequency doubler circuit is designed as an application of the proposed multiplier/divider circuit and the transient analysis of this circuit is given in this study. Absolute error of the current function of the frequency doubler circuit is observed. The proposed method enables the use of much smaller transistors and the circuits to be designed are smaller than their counterparts. Thus they may be operated at much higher frequencies. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. The proposed circuit is appropriate to be used for filtering in square root domain, fuzzy logic controllers, artificial neural networks, modulators, phase discriminators, adaptive filters, RMS-DC converters, sine/cosine synthesizers, cryptography systems etc. Keywords: reduction MOSFET's second order effects, square root circuit, squarer/divider circuit, multiplier circuit, frequency doubler