Building Benchmark Designs For Trojan Experiments

Hardware manufacturers are increasingly outsourcing their Integrated Circuits (IC) fabrication to offshore facilities, due to the global economic business pressures. These facilities are geographically dispersed and are typically outside the control of known trusted sources, which makes the ICs vulnerable to malicious modi?cations. Adversaries can modify the systems to circumvent the security and encryption, trigger based on certain data patterns, and incapacitate critical systems like radar at crucial times. The malicious alterations and inclusions made by adversaries to the IC during fabrication are known as Trojans.There is a considerable interest in the academic community to develop Trojan detection methods. But, currently there are no benchmark designs to evaluate, compare and contrast these different Trojan detection methods. In this work, a design ?ow known as the Iterative Restrictive and Replacement (IRR) technique was developed to design and build small-to-large benchmark physical layouts for Trojan-based insertion and detection experiments. The IRR technique was successfully applied to build a medium-to-large benchmark design. This design is based on a 5-stage pipelined MIPS microprocessor and incorporates Design For Hardware Trust (DFHT) support for Rad et al. [10] proposed power supply transient signal analysis method to detect defects, and host Trojans at various locations in the IC. Further work could involve developing more benchmark circuits, fabrication and validation in silicon