Methodology for Analyzing ESD-Induced Soft Failure using Full-Wave Simulation and Measurement

An analysis methodology is presented to investigate soft failures in electronic devices. This methodology combines transmission line pulse (TLP) full-wave simulations with system-level and TLP measurements. Information on susceptible parts in the device under test (DUT) and/or soft failure sensitivity of the integrated circuits (ICs) are obtained from the measurements. Then, the TLP current spreading within the printed circuit board (PCB) of the DUT is simulated. The susceptible signals can be determined by comparing the simulated voltages and/or currents at the signal terminations with the measured threshold values. If the simulated voltages and/or currents are higher than the threshold values, the signal is considered susceptible and a soft failure may occur in the DUT. Using the obtained information from simulations and measurements, the root causes of soft failures can be identified. Further, by utilizing full-wave simulations, the design of the product can be modified to reduce the electrostatic discharge (ESD) noise on the susceptible signals, and consequently prevent soft failures. The proposed analysis methodology is applied to a tablet which suffers from soft failure. The root cause of the soft failure is identified, and countermeasures are designed against the ESD-induced soft failure