Modeling Interference Coupling between Two Orthogonal Strip Lines on Adjacent Layers

In multi-layer circuit boards of modern electronic equipment, signal lines and power distribution traces can be set orthogonally and sandwiched between two reference layers. To evaluate interference between such a intersecting strip line geometry, a lumped mutual capacitance model is proposed. Determining the scalar potential due to an assumed line charge at the intersection of the orthogonal traces leads to the distributed mutual capacitance between two lines. The results show that for typical printed circuit board geometries, the mutual capacitance can be approximated as a lumped element at the intersection of the two orthogonal strip line geometries. The proposed model is verified by comparing experimental and the computed results