In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characterization by using a set of simple yet efficient test patterns. For all the test patterns, full wave models are developed and the electrical performance of the test patterns is analyzed thoroughly. Furthermore, broadband measurements are performed for the test patterns to verify the accuracy of the developed full wave models up to 40 GHz. Correlation between measurement and simulation results is discussed after optimizing the full wave models based on scanning electron microscope measurement. Analysis of measurement error is available as well. The proposed de-embedding method is applied to both the simulation and measurement results to extract t...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
Includes bibliographical references (p. 42-45)The 3D IC integration technology and silicon interpose...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characteri...
In this paper, a de-embedding method to extract the performance of a Through-Silicon-Via (TSV) pair ...
In this paper, practical test patterns are designed to calculate the characteristics of Through-Sili...
Traditional two-dimensional system-in-package (2D SiP) can no longer support the scaling of size, po...
In this paper, analytical, numerical-, and measurement-based methods for extracting the resistance, ...
Measurement-based electrical characterization of through silicon via (TSV) and redistribution layer ...
Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extract t...
One of the most important aspects of modern electronic designs is device measurement and characteriz...
Silicon interposer technology with through-silicon-vias will play a significant role in the developm...
To support the recent progress in 3-D integration based on through-silicon via (TSV) technology, an ...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
Includes bibliographical references (p. 42-45)The 3D IC integration technology and silicon interpose...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characteri...
In this paper, a de-embedding method to extract the performance of a Through-Silicon-Via (TSV) pair ...
In this paper, practical test patterns are designed to calculate the characteristics of Through-Sili...
Traditional two-dimensional system-in-package (2D SiP) can no longer support the scaling of size, po...
In this paper, analytical, numerical-, and measurement-based methods for extracting the resistance, ...
Measurement-based electrical characterization of through silicon via (TSV) and redistribution layer ...
Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extract t...
One of the most important aspects of modern electronic designs is device measurement and characteriz...
Silicon interposer technology with through-silicon-vias will play a significant role in the developm...
To support the recent progress in 3-D integration based on through-silicon via (TSV) technology, an ...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...
Includes bibliographical references (p. 42-45)The 3D IC integration technology and silicon interpose...
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrica...