Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory System

This paper discusses the issues of FPGA reconfigurable memory system with faulty physical memory cells and yield measurement techniques are proposed. Static yield and dynamic yield of FPGA reconfigurable memory systems and their characteristics are analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations and redundant memory cells, if any, can be used as spares to enhance dynamic yield of the target memory configuration. Three fundamental strategies are introduced and analyzed: redundant bits, redundant words and combination of both. Mathematical analysis of those techniques also has been conducted to clarify their effects on yield. Selecting the most yield enhancing logical memory configuration which can accommodate the given target memory requirement among candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system (SRS) fitting and concurrent reconfiguration system (CRS) fitting are proposed and analyzed based on the yield analysis techniques