Add to ORKGThis paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous null convention logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18mum TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NU...
This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Thresho...
Testing of an electronic chip is an important step in the design process, as it can detect faults an...
This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using...
In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e....
This thesis focuses on design and characterization of arithmetic circuits, such as multipliers and A...
Two versions of a reconfigurable logic element are developed for use in constructing afield-programm...
The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design met...
Self-timed multipliers, designed using the delay-insensitive null convention logic (NCL) paradigm, w...
The increasing power consumption in the synchronous circuits is the major concern in the semiconduct...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-stat...
Self-timed properly judgment layout strategies are advanced the usage of Threshold Combinational Red...
In recent years, crosstalk noise has emerged a serious problem because more and more devices and wir...
This thesis focuses on designing generic quad-rail arithmetic circuits, such as signed and unsigned ...
This Master\u27s thesis is intended to familiarize the reader with the asynchronous delay-insensitiv...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NU...
This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Thresho...
Testing of an electronic chip is an important step in the design process, as it can detect faults an...
This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using...
In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e....
This thesis focuses on design and characterization of arithmetic circuits, such as multipliers and A...
Two versions of a reconfigurable logic element are developed for use in constructing afield-programm...
The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design met...
Self-timed multipliers, designed using the delay-insensitive null convention logic (NCL) paradigm, w...
The increasing power consumption in the synchronous circuits is the major concern in the semiconduct...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-stat...
Self-timed properly judgment layout strategies are advanced the usage of Threshold Combinational Red...
In recent years, crosstalk noise has emerged a serious problem because more and more devices and wir...
This thesis focuses on designing generic quad-rail arithmetic circuits, such as signed and unsigned ...
This Master\u27s thesis is intended to familiarize the reader with the asynchronous delay-insensitiv...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NU...
This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Thresho...
Testing of an electronic chip is an important step in the design process, as it can detect faults an...