Add to ORKGAs the complexities of NULL Convention Logic circuits increase, the crucial role of design automation tools in virtually every aspect of NCL circuit design is undeniable. This thesis focuses on the design of several tools that can be used along with one of the industry standard digital design tool suites, Mentor Graphics, to automate and speedup the NCL design process. Hence, the tools are implemented at Tcl scripts, which can be run from within the Mentor Graphics toolset. --Abstract, page iii
This thesis focuses on describing the method for simulating transistor-level design with a VHDL test...
This book is designed to serve as a hands-on professional reference with additional utility as a tex...
While asynchronous techniques are of increasing interest in low-power design, designers cannot simpl...
This M.S. thesis is intended to familiarize the reader with the syntax and semantics of NULL Convent...
This dissertation focuses on developing algorithms for design automation of asynchronous NULL Conven...
This thesis presents an implementation of a method developed to readily convert Boolean designs into...
The Null Convention Logic (NCL) based asynchronous design technique has interested researchers becau...
As clock skew and power consumption become major challenges in deep submicron design of synchronous ...
Design flow and technique in many respects define quality and time cost of custom integrated circuit...
This Master\u27s thesis is intended to familiarize the reader with the asynchronous delay-insensitiv...
Self-timed properly judgment layout strategies are advanced the usage of Threshold Combinational Red...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
ARTICLE IN PRESS Self-timed logic design methods are developed using Threshold Combinational Reducti...
This thesis focuses on describing the method for simulating transistor-level design with a VHDL test...
This book is designed to serve as a hands-on professional reference with additional utility as a tex...
While asynchronous techniques are of increasing interest in low-power design, designers cannot simpl...
This M.S. thesis is intended to familiarize the reader with the syntax and semantics of NULL Convent...
This dissertation focuses on developing algorithms for design automation of asynchronous NULL Conven...
This thesis presents an implementation of a method developed to readily convert Boolean designs into...
The Null Convention Logic (NCL) based asynchronous design technique has interested researchers becau...
As clock skew and power consumption become major challenges in deep submicron design of synchronous ...
Design flow and technique in many respects define quality and time cost of custom integrated circuit...
This Master\u27s thesis is intended to familiarize the reader with the asynchronous delay-insensitiv...
Self-timed properly judgment layout strategies are advanced the usage of Threshold Combinational Red...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
ARTICLE IN PRESS Self-timed logic design methods are developed using Threshold Combinational Reducti...
This thesis focuses on describing the method for simulating transistor-level design with a VHDL test...
This book is designed to serve as a hands-on professional reference with additional utility as a tex...
While asynchronous techniques are of increasing interest in low-power design, designers cannot simpl...