Simulation of a 0.6 V Wideband CMOS LNA Design Using Forward Body Bias

A 0.6-V wideband Low-Noise Amplifier (LNA) design using a 0.18 μm CMOS standard process is presented in this paper. An important goal for the design is to achieve wideband under a low supply voltage. The presented LNA design is a three-stage amplifier, which is based on a common gate stage and two common source stages. The common gate stage provides a wideband input matching. The two common source stages provide a flat gain. A forward body bias technique is used to reduce the supply voltage of the wideband LNA. The forward body bias, that is, the body-source voltage (VBS) is greater than 0 V, decreases the threshold voltage of the NMOS transistor, achieving the low voltage LNA. The supply voltage that is applied to the wideband LNA is only 0.6 V and the Power Consumption (PDC) is 9.24 mW. Simulation results indicate that the gain exceeds 10 dB and the Noise Figure (NF) is below 6.5 dB from 1.62 GHz to 7.02 GHz. The main advantage of the LNA is it's wideband with a low supply voltage