Add to ORKGThis paper proposes a design guideline for the aspect ratio (Rh/w) of the fin height (h) to fin width (w) of 3-D devices (FinFET like double-gate (DG) FET and triple-gate (TG)-FET) that is based on device simulations. Since any change in the aspect ratio yields the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing 3-D architectural devices. We found that the increase in w seems to bring a high drive current (Ion) and an enhancement of Ion, but that a large w is undesirable for shorter channel length (L) devices because the drain-induced barrier lowering (DIBL) effect is enhanced ; TG-FET is superior to FinFET in terms of both drivability and short-channel eff...
This paper presents an investigation on properties of Double Gate FinFET (DG-FinFET) and impact of p...
This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs...
The intensive downscaling of MOS transistors has been the major driving force behind the aggressive ...
This paper proposes a design guideline for the aspect ratio (Rh/w) of the fin height (h) to fin widt...
DoctorThe development of silicon planar technology over the past half-century has been one of the mo...
This paper presents a simulation study on the gate length scaling of a double gate (DG) FinFET. To a...
An SOI MOSFET with FINFET structure is simulated using a 3-D simulator. I-V characteristics and sub-...
In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate S...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend...
MOSFETs with multiple gate structures, such as 3-D FinFETs have seen enormous interest for sub-22 nm...
Si SOI FinFETs with gate lengths of 12.8 nm and 10.7 nm are modelled using 3D Finite Element Monte C...
The high-k is needed to replace SiO2 as the gate dielectric to reduce the gate leakage current. The ...
Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting ga...
This paper presents an investigation on properties of Double Gate FinFET (DG-FinFET) and impact of p...
This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs...
The intensive downscaling of MOS transistors has been the major driving force behind the aggressive ...
This paper proposes a design guideline for the aspect ratio (Rh/w) of the fin height (h) to fin widt...
DoctorThe development of silicon planar technology over the past half-century has been one of the mo...
This paper presents a simulation study on the gate length scaling of a double gate (DG) FinFET. To a...
An SOI MOSFET with FINFET structure is simulated using a 3-D simulator. I-V characteristics and sub-...
In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate S...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend...
MOSFETs with multiple gate structures, such as 3-D FinFETs have seen enormous interest for sub-22 nm...
Si SOI FinFETs with gate lengths of 12.8 nm and 10.7 nm are modelled using 3D Finite Element Monte C...
The high-k is needed to replace SiO2 as the gate dielectric to reduce the gate leakage current. The ...
Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting ga...
This paper presents an investigation on properties of Double Gate FinFET (DG-FinFET) and impact of p...
This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs...
The intensive downscaling of MOS transistors has been the major driving force behind the aggressive ...
