LOW POWER CONSUMED MULTIPLIER DESIGN BY ANT ARCHITECTURE WITH FIXED WIDTH REPLICA REDUNDANCY BLOCK

In this paper, we propose a dependable low-control multiplier configuration by receiving algorithmic commotion tolerant (ANT) engineering with the settled width multiplier to assemble the lessened accuracy copy excess square (RPR). The proposed ANT engineering can take care of the demand of high accuracy, low power utilization, and zone proficiency. We plan the settled width RPR with mistake remuneration circuit by means of examining of likelihood and insights. Utilizing the halfway item terms of information remedy vector and minor info redress vector to bring down the truncation blunders, the equipment unpredictability of mistake pay circuit can be improved. In a 12 × 12 bit ANT multiplier, circuit zone in our settled width RPR can be brought down by 44.55% and control utilization in our ANT configuration can be spared by 23% as contrasted and the condition of-workmanship ANT outline