AN OPTIMIZED AREA AND DELAY PARALLEL PREFIX TREE METHODOLOGY FOR QUANTUM-DOT CELLULAR AUTOMATA

Quantum-dot cellular automata (QCA) are a conspicuous technology suitable for the development of ultra-dense-low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. In this paper area and power optimized QCA comparator is presented for developing a 32bit full comparator. It is able to achieve lower area and power consumption. With respect to existing counterparts the comparators proposed here exhibit significantly higher speed and reduced overall area and power. The structures proposed in provide higher computational capabilities, and circuits able to separately recognize all the three possible conditions i.e., a = b, a > b, and a < b. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. The proposed scheme, we deal with 32-bit numbers with less number of resources unlike conventional comparators, which leads to the realization of low power and area efficient comparator. This comparator can be widely used in central processing units (CPUs) and microcontrollers