DESIGN AND IMPLEMENTATION OF LOW POWER TRUNCATED MULTIPLIER BY ADOPTING ANT ARCHITECTURE USING FIXED-WIDTH RPR BLOCK

The suggested ANT architecture can satisfy the need for high precision, low power consumption, and area efficiency. To reduce the ability dissipation, supply current scaling is broadly used as a good low-power technique because the power consumption in CMOS circuits is proportional towards the square of supply current. While using partial product relation to input correction vector and minor input correction vector to reduce the truncation errors, the hardware complexity of error compensation circuit could be simplified. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Within this paper, we advise a dependable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture using the fixed-width multiplier to construct the lower precision replica redundancy block (RPR). Inside a 12 × 12 bit ANT multiplier, circuit area within our fixed-width RPR could be decreased and power consumption within our ANT design could be saved, in contrast to the condition-of-art ANT design