A CLATTER LIBERAL FRAMEWORK TO CONSTRUCT REPLICA BLOCK

We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. While using partial product relation to input correction vector and minor input correction vector to reduce the truncation errors, the hardware complexity of error compensation circuit could be simplified. Within this paper, we advise a dependable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture using the fixed-width multiplier to construct the lower precision replica redundancy block (RPR). The reduced-current low-power merit within the presented ANT design can nonetheless be preserved under process deviation and-temperature environments. Under lower Kvos, the ability consumption could be decreased. The suggested ANT architecture can satisfy the need for high precision, low power consumption, and area efficiency. Within an ANT multiplier, circuit area within our fixed-width RPR could be decreased and power consumption within our ANT design could be saved compared to the condition-of-art ANT design. The RPR area is yet another main factor which will modify the power saving. The truncated RPRs are examined from word period of 5 to 10 bits using Synopsys design complier CAD tool. Hence, we compare the circuitry area occupied through the fixed-width RPR multiplier and also the full-width RPR multiplier