DESIGN OF MAC WITH IMPROVEMENT IN PERFORMANCE

In this paper a new technique is proposed and implemented by the help of the accumulator oriented multiplier and termed as the protocol of the MAC with the improved performance of the storage of the 64 bit data. The performance of the unit related to the MAC protocol is integrated by the help of the processor of the digital signal for the evaluation of the operation related to the unit of MAC plays a crucial role in its analysis point of view respectively. Here the design of the multiplier based on the modified multiplier wallace adder of the carry save is used as the adder operationality respectively. The implementation of the proposed system is in the language of the source code of the VHDL and the compiler of the RTL cadence is used for the synthesis effectivity under the technology of the TSMC of the included library functions in a typical fashion. Here implementation is in such a way that there is a reduced dissipation of the power at the time of the analysis and the implementation structure and design based criteria. Experiments have been conducted on the present method where there is a lot of analysis takes place on the present method in which a huge number of test beds have been conducted for the calculation of the performance of the system in a well oriented fashion respectively