Flexible Multi-ASIP SoC for High-Throughput Turbo Decoders

International audienceApplications in the field of digital communications are becoming more and more diversified and complex. This trend is driven by the emergence of turbo-communications which generalize the principle of iterative processing introduced by the turbo-codes. Implementation of turbo-communication systems -such as channel decoding, equalization, demodulation, synchronization or MIMO systems- is becoming crucial to reach the nowadays performance requirements in terms of transmission quality (e.g. throughput and error rates). However, the severe time-to-market constraints and the continuously developing new standards and applications in this field, make resorting to new design methodologies and the proposal of a flexible turbo communication platform inevitable. Flexibility and high-throughput requirements are being widely investigated in this application domain during the last few years. Several implementations have also been proposed. Some of these implementations succeeded in achieving high throughput for specific standards with a highly dedicated architecture. However, these implementations do not take into account flexibility and scalability issues. Conversely, others implementations include software and/or reconfigurable parts to achieve the required flexibility while achieving much lower throughput. In this work, our aim is to tackle flexibility and performance requirements simultaneously by proposing multiprocessor architectures dedicated to turbo-communications. The architecture models we are proposing are based on Application-Specific Instruction-set Processors (ASIP) interacting through an adequate communication network in a multi-ASIP architecture platform