Flexible and scalable on-chip communication network for multiprocessor turbo decoding

International audiencePresent and future digital communication standards in the field of wireless communication, fiber-optic communication and storage applications are proposing more and more the use of turbo codes as error correcting codes. In this application domain, flexibility and high-throughput requirements are being widely investigated during the last few years. In this context, multiprocessor platforms constitute a promising architectural solution for the design of high-throughput flexible turbo decoders. Besides application algorithm optimizations and application-specific processor design, the on-chip communication network connecting the multiple on-chip cores constitutes a major issue. Our aim in this work is to propose a network-on-chip architecture allowing efficient multiprocessor turbo decoder implementation. Proposed NoC architectures should accommodate the intensive and random extrinsic information exchange between the iterative processing components. Scalability is required in order to cope with the increasingly severe constraints in terms of throughput and error rates, while flexibility is required in order to support any interleaving rule, and thus, any application standard. In this context, appropriate flexible and scalable application-specific NoC topologies, routing algorithms and resources management techniques are being proposed