Spéculation temporelle algorithmique pour accélérateurs de réseaux de neuro

In this paper, we propose a technique for improving the efficiency of hardwareaccelerators based on timing speculation (overclocking) and fault tolerance. We augment theaccelerator with a lightweight error detection mechanism to protect against timing errors, enablingaggressive timing speculation. We demonstrate the validity of our approach for the convolutionlayers in Convolutional Neural Networks (CNN). We present an implementation of a fault-tolerantCNN accelerator combined with the lightweight error detection for convolution layers. The errordetection mechanism we have developed works at the algorithm level, based on algebraic propertiesof the computation, allowing the full implementation to be realized using High-Level Synthesistools. We use a set of Zybo boards to experimentally demonstrate that overclocking boosts thefrequency by 17-36% with low chances of error, and that the infrequent errors can be detected witha negligible overhead (only 1000 LUTs)