Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

International audienceThrough-Silicon-Vias (TSV) are the key to 3D integrated microsystems. Their fabrication leads to reliability issues linked to the thermo-mechanical stress induced in the silicon around the vias. In this work, we propose to reduce the silicon residual stress in high aspect ratio copper TSVs (HAR TSV) using an electrografted polymer insulator, poly-4-vinylpyridine (P4VP), in replacement of the traditional silicon oxide layer. We use Raman spectroscopy to make the first investigation of the residual stress in the Si around P4VP insulated TSVs and compare it to SiO2 insulated TSVs. The results show that P4VP acts as a stress buffer layer because of its particular mechanical properties as the measured residual stress in Si is significantly reduced at room temperature around the polymer insulated HAR TSVs. The potential benefits of such a technology are not only a better thermo-mechanical reliability of 3D integrated microsystem, but also a greater integration density