Low loss Si-substrates enhanced using buried PN junctions for RF applications

A novel method for increasing the effective resistivity in low-doped silicon substrates is presented. By creating a chain series of p-n depletion junctions beneath the insulator, the parasitic surface conduction channel is interrupted, significantly lowering substrate losses and reducing harmonic distortion in the simulated and measured CPW lines achieving performance close to the widely used trap-rich silicon substrate at RF frequencies