High-level implementation of a partial DSP algorithm chain used in a digital radio using functional programming

This thesis investigates the advantages of using functional programming as a hardware description tool. The functional programming paradigm shares a lot of similarities with hardware, as it is highly parallel in nature and has a notion of structure in its descriptions. Furthermore, it operates on a higher-level of abstraction compared to commonly-used hardware description languages, which facilitates the design- and debugging process. The thesis explores the Viterbi decoder in detail, and looks at related hardware implementation techniques. The decoder is implemented in the functional programming language Haskell, and transformed to a synthesizable SystemVer- ilog description with a tool known as CLaSH. The generated solution is verifed with testbenches made for a reference design, provided by Nordic Semiconductor. Furthermore, the CLaSH generated implementation is synthesized and the quality is compared with the reference design, in terms of resource utilization and performance