Improving Reusability in SoC Project Verification Flow

This main target of the thesis is to increase the level of reuse done in SoC verification projects. The verification takes the biggest amount of time in the project duration. This thesis contains 3 main parts. The first one introduces the reuse in SoC and explains its different dimensions as a literature study. This work is done as a background for the next two phases. During the second part of this work, a practical example for verification reuse was implemented as a part of a SoC project. The reuse was applied vertically, where an IP-level testbench was altered to become reusable, then it was reused in a subsystem-level testbench. Additionally, analysis was done in order to know how much effort was reused in the project. Results show that 85% of the code was saved when the reuse was applied. Regarding the third part of the thesis, several interviews were conducted with SoC verification experts who work at Nokia with a range of experience in the field from 7 to 20 years. These interviews were done in order to collect some information about how to improve the reusability in SoC project verification flow. The point from these interviews is to get knowledge from hands-on-experience. The interviewees agreed on the importance for applying the reuse in every verification project from the beginning of the project. They also agreed on maintaining the hierarchical level of reuse, which means IP-level TB would be a sub-environment of subsystem-level TB and subsystem-level is a sub-environment of SoC-level TB. Moreover, some ideas about the future work are introduced here. Those are proposed according to the knowledge gained from the research and from the interviews with the experts