A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

Event: SPIE/IS&T Electronic Imaging, 2015, San Francisco, California, United StatesThe design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reverse start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.Office of Naval Research (USA) ONR, grant No. N000141410355Ministerio de Economía y Competitividad TEC2012-38921-C02, IPT-2011-1625- 430000, IPC-20111009 CDTIJunta de Andalucía TIC 2012-233