Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications
- Sassine, Gilbert
- Nail, Cecile
- Tillie, Luc
- Robayo, Diego Alfaro
- Levisse, Alexandre
- Cagli, Carlo
- Hajjam, Khalil El.
- Nodin, Jean-François
- Vianello, Elisa
- Bernard, Mathieu
- Molas, Gabriel
- Nowak, Etienne
Publication date
March 2018
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
International audienceIn this paper, programming operations are optimizedfor low energy consumption and short latency time applicationsin RRAM kb arrays. Origin of consumption (role of pulse’stime, programming current and voltage in SET and RESEToperations) is quantified on HfO$_2$ oxide based RRAMtechnology. Specific patterns are evaluated to reduce latencytime and energy consumption in memory devices. Innovativecircuit with $on\ the\ fly$ switching detection is proposed, allowingto reduce programming consumption down to single pJoperation in large memory arrays
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