none5siEnergy efficiency is a crucial aspect in modern SoCs. Common strategies like aggressive voltage scaling and parallel processing have enabled major improvements in active energy efficiency. However, the big impact of process variations, as well as the temperature sensitivity of devices operating in near threshold force digital designers to adopt very conservative margins for timing closure.openDi Mauro, Alfio; Rossi, Davide; Pullini, Antonio; Flatresse, Philippe; Benini, LucaDi Mauro, Alfio; Rossi, Davide; Pullini, Antonio; Flatresse, Philippe; Benini, Luc
27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Ha...
This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI t...
Ces dix dernières années, la miniaturisation des transistors MOS en technologie planaire sur siliciu...
none5siTo provide high computational capabilities, and, at the same time, minimize the power consum...
Environmental temperature variations, as well as process variations, have a detrimental effect on pe...
none5siAdvanced Ultra-Low Power (ULP) computing platforms can be affected by large performance varia...
The performance and reliability of Ultra-Low-Power (ULP) computing platforms are adversely affected ...
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high...
partially_open7siNome progetto: MultithermanA 4-core cluster fabricated in low power 28nm UTBB FD-SO...
As technology scales down in order to meet demands of more computing power per area, a variety of ch...
Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioratio...
International audienceThe emerging SOI technologies provide an increased body bias range compared to...
L'efficacité énergétique est devenue une métrique clé de la performance des systèmes sur puce numéri...
none8siAs technology edges closer to fundamental limits, variations of process parameters, operation...
27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Ha...
This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI t...
Ces dix dernières années, la miniaturisation des transistors MOS en technologie planaire sur siliciu...
none5siTo provide high computational capabilities, and, at the same time, minimize the power consum...
Environmental temperature variations, as well as process variations, have a detrimental effect on pe...
none5siAdvanced Ultra-Low Power (ULP) computing platforms can be affected by large performance varia...
The performance and reliability of Ultra-Low-Power (ULP) computing platforms are adversely affected ...
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high...
partially_open7siNome progetto: MultithermanA 4-core cluster fabricated in low power 28nm UTBB FD-SO...
As technology scales down in order to meet demands of more computing power per area, a variety of ch...
Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioratio...
International audienceThe emerging SOI technologies provide an increased body bias range compared to...
L'efficacité énergétique est devenue une métrique clé de la performance des systèmes sur puce numéri...
none8siAs technology edges closer to fundamental limits, variations of process parameters, operation...
27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Ha...
This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI t...
Ces dix dernières années, la miniaturisation des transistors MOS en technologie planaire sur siliciu...