The OpenRISC processor core, featuring a flat pipeline and a low area footprint has been integrated in a multi-core ultra-low power (ULP) cluster with a shared multi-banked memory to exploit parallelism in the near-threshold regime. The micro-architecture has been optimized to support a shared L1 memory and to achieve a high value of instructions per cycle (IPC) per core. The proposed architecture achieves IPC results in the range of 0.88 and 1 in a set of benchmark applications which is an improvement of up to 83% with respect to the original OpenRISC implementation. Implemented in 28nm FDSOI technology, the proposed design achieves 177 MOPS when supplied at 0.6V near-threshold voltage. The energy efficiency at this workload is 90.07 MOPS/...
open5siDate of Publication: 02 November 2017High performance and extreme energy efficiency are stron...
This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) em...
open6siThe steeply growing performance demands for highly power- and energy-constrained processing s...
The OpenRISC processor core, featuring a flat pipeline and a low area footprint has been integrated ...
none8siNome progetto: NanoTeraBaseline RISC instruction sets for ultra-low power processors are cons...
L1 instruction caches in many-core systems represent a siz-able fraction of the total power consumpt...
Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal proc...
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high...
partially_open7siNome progetto: MultithermanA 4-core cluster fabricated in low power 28nm UTBB FD-SO...
The stringent power constraints of complex microcontroller based devices (e.g. smart sensors for the...
The stringent power constraints of complex microcontroller based devices (e.g. smart sensors for the...
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high...
open5siDate of Publication: 02 November 2017High performance and extreme energy efficiency are stron...
This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) em...
open6siThe steeply growing performance demands for highly power- and energy-constrained processing s...
The OpenRISC processor core, featuring a flat pipeline and a low area footprint has been integrated ...
none8siNome progetto: NanoTeraBaseline RISC instruction sets for ultra-low power processors are cons...
L1 instruction caches in many-core systems represent a siz-able fraction of the total power consumpt...
Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal proc...
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high...
partially_open7siNome progetto: MultithermanA 4-core cluster fabricated in low power 28nm UTBB FD-SO...
The stringent power constraints of complex microcontroller based devices (e.g. smart sensors for the...
The stringent power constraints of complex microcontroller based devices (e.g. smart sensors for the...
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high...
open5siDate of Publication: 02 November 2017High performance and extreme energy efficiency are stron...
This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) em...
open6siThe steeply growing performance demands for highly power- and energy-constrained processing s...