FPGA design and performance evaluation of a pulse-based echo canceller for DVB-T/H

Different design issues and performance aspects of a low-complexity echo canceller for digital on-channel repeaters are described in this paper. Locally generated pulse trains are injected in the repeated signal to estimate the coupling channel between the transmitting and the receiving antennas. In particular, we analyze a low-complexity channel cancellation technique based on the reconstruction of the coupling channel pulse response via digital FIR filtering. After developing a proper theoretical model, the analytical expressions of some important performance figures are determined, e.g. the Mean Rejection Ratio and the Echo Suppression at Nominal Position. Then, the description of our implementation of the echo canceller on a FPGA board is reported. Finally, the performance values derived by the theoretical model are compared to measurements results