Soft-core embedded-FPGA based on multistage switching networks: a quantitative analysis

Embedded field programmable gate arrays (eFPGA) can provide modern systems-on-a-chip (SoCs) with the flexibility required to face the growth of nonrecurring engineering and manufacturing costs. On the other hand, SoC designers usually perceive eFPGAs as area-hungry IPs with poor flexibility in terms of performance, power and area tradeoff since they are typically available as custom-designed hard macros. In this scenario, technology scaling is allowing designers to reduce the impact of the eFPGA area gap, while effective exploitation of all the technology options (e.g., the transistor threshold) entails moving toward soft-core eFPGAs to match specific application needs. In this paper, we propose an look-up table-based soft-core eFPGA featuring a synthesizable and parametric architecture. A key point of our proposal is that we have adopted a multistage switching network (MSSN) to implement the programmable interconnect, since this ensures a synthesizable and congestion-free architecture. Quantitative evaluation of our eFPGA shows a significantly wide design-space available on very different technologies (we experimented STMicroelectronics CMOS 65 nm and BCD9s 0.11 μm). Application-driven evaluation showed how for a fixed eFPGA size (i.e., number of logic blocks) different configurations of the MSSN allow designers to speed up performance by 20/60%, as well as to maximize the computational density for a given area budget