In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations exist. To this end, a single- and a multi-core architecture are proposed and compared. The single-core architecture is composed of one ULP processing core, an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of several ULP processing cores, individual IMs for each core, a shared DM and an interconnection crossbar between the cores and the DM. These architectures are compared with respect to power/performance trade-offs for different target workloa...
University of Minnesota Ph.D. dissertation. July 2012. Major: Electrical Engineering. Advisor: Kesha...
Energy efficient processing architectures represent key elements for wearable and implantable medica...
The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which...
In this study, the authors explore sequential and parallel processing architectures, utilising a cus...
none5This study presents a single-core and a multi-core processor architecture for health monitoring...
This study presents a single-core and a multi-core processor architecture for health monitoring syst...
A multi-core architecture with ultra-low power consumption is needed for a wide variety of applicati...
This paper introduces a novel computing architecture devoted to the ultra-low power analysis of mult...
In the last decade, improvements on technology scaling have enabled the design of a novel generation...
In the last years, remote health monitoring is becoming an essential branch of health care with the ...
In the last years, remote health monitoring is becoming an essential branch of health care with the ...
Abstract — As the study of the wireless body area sensor network (BASN) keeps growing, corresponding...
Technology scaling enables today the design of sensor-based ultra-low cost chips well suited for eme...
This paper introduces an inexact, but ultra-low power, computing architecture devoted to the embedde...
\u3cp\u3eThis paper presents a voltage-scalable digital signal processing system designed for the us...
University of Minnesota Ph.D. dissertation. July 2012. Major: Electrical Engineering. Advisor: Kesha...
Energy efficient processing architectures represent key elements for wearable and implantable medica...
The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which...
In this study, the authors explore sequential and parallel processing architectures, utilising a cus...
none5This study presents a single-core and a multi-core processor architecture for health monitoring...
This study presents a single-core and a multi-core processor architecture for health monitoring syst...
A multi-core architecture with ultra-low power consumption is needed for a wide variety of applicati...
This paper introduces a novel computing architecture devoted to the ultra-low power analysis of mult...
In the last decade, improvements on technology scaling have enabled the design of a novel generation...
In the last years, remote health monitoring is becoming an essential branch of health care with the ...
In the last years, remote health monitoring is becoming an essential branch of health care with the ...
Abstract — As the study of the wireless body area sensor network (BASN) keeps growing, corresponding...
Technology scaling enables today the design of sensor-based ultra-low cost chips well suited for eme...
This paper introduces an inexact, but ultra-low power, computing architecture devoted to the embedde...
\u3cp\u3eThis paper presents a voltage-scalable digital signal processing system designed for the us...
University of Minnesota Ph.D. dissertation. July 2012. Major: Electrical Engineering. Advisor: Kesha...
Energy efficient processing architectures represent key elements for wearable and implantable medica...
The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which...