VDD scalability of FinFET SRAMs: robustness of different design options against LER-induced variations

Replacing the conventional MOSFET architecture with multiple gate structures like the FinFET can improve scalability of SRAM circuits, especially in low-voltage/low-power applications. The impact of fin line-edge roughness (LER) on noise margins of LSTP- and LOP-32 nm compatible FinFET SRAMs is systematically investigated at different supply voltages to assess VDD scalability of these cells. Read and write noise margins are computed by performing mixed-mode simulations featuring quantum-corrected hydrodynamic transport models on large Monte Carlo ensembles. A restrictive yield criterion is used to compare several design options, including transistor sizing, mobility changes as a result of crystal orientation, fin patterning and gate stack, and VT tuning through work function (WF) engineering. Confidence intervals are provided to account for ensemble size related statistical noise. Based on simulation results and comparison with published measurements, guidelines are provided to trade-off design options for improved LER robustness and VDD scalability of FinFET SRAMs