Automatic synthesis of near-threshold circuits with fine-grained performance tunability

Near-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. In this work, we tackle this problem by proposing a novel dual-Vdd technique for near-threshold operation and show that one can tune the performance of a circuit in a fine-grained manner by powering an optimal sub-set of rows with a slightly higher supply voltage than the rest, without incurring the large cost of distributed level shifters. By varying the percentage of rows at a slightly higher voltage, one can trade-off performance and power in a fine-grained manner. Experimental results show that by employing our dual-Vdd technique, we can improve the performance of several benchmarks up-to 45% while achieving more than 50% lower power as compared to single-Vdd implementations