The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs is estimated through TCAD simulations. A Monte Carlo approach highlights an increase in the average VT and a decrease in the average ION w.r.t. sensitivity analysis based predictions. Correlations of fin shape fluctuations to electrical performance are investigated. An equivalent fin width is calculated, which allows reducing the spread in ION scatter plots and highlights relative importance of LER in different fin regions. Simplified device instances with linearly varying fin width are simulated to better assess the impact of local thinning/thickening in the channel, S and D extensions, revealing asymmetries in the device behavior upon sw...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. ...
This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate F...
Line-edge roughness induced fin-edge roughness (FER) is the primary source of V-T variation in FinFE...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs i...
Threshold voltage ðVT Þ and drive current ðIONÞ variability of low stand-by power (LSTP)-32 nm FinFE...
While traditional scaling used to be accompanied by an improvement in device performance, this is mu...
Replacing the conventional MOSFET architecture with multiple gate structures like the FinFET can imp...
3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs ...
none4Short-range process variations such as line-edge roughness (LER) and random dopant fluctuations...
FinFETs may start to replace planar MOSFETs for specific applications at the 32nm node and beyond du...
FinFET is a promising architecture for low voltage/low-power applications at and beyond the 32nm tec...
3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughnes...
This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFE...
Variability is a critical concern for the stability and yield of SRAM with minimized size. We prese...
none5Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Am...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. ...
This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate F...
Line-edge roughness induced fin-edge roughness (FER) is the primary source of V-T variation in FinFE...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs i...
Threshold voltage ðVT Þ and drive current ðIONÞ variability of low stand-by power (LSTP)-32 nm FinFE...
While traditional scaling used to be accompanied by an improvement in device performance, this is mu...
Replacing the conventional MOSFET architecture with multiple gate structures like the FinFET can imp...
3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs ...
none4Short-range process variations such as line-edge roughness (LER) and random dopant fluctuations...
FinFETs may start to replace planar MOSFETs for specific applications at the 32nm node and beyond du...
FinFET is a promising architecture for low voltage/low-power applications at and beyond the 32nm tec...
3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughnes...
This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFE...
Variability is a critical concern for the stability and yield of SRAM with minimized size. We prese...
none5Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Am...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. ...
This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate F...
Line-edge roughness induced fin-edge roughness (FER) is the primary source of V-T variation in FinFE...