LER-induced limitations ti VDD scalability of FinFET-based SRAMs with different design options

FinFET is a promising architecture for low voltage/low-power applications at and beyond the 32nm technology generation. VDD scalability of LSTP- and LOP-32nm compatible FinFET SRAMs is investigated in the presence of fin line-edge roughness (LER). Several design options are compared, including transistor sizing, mobility changes as a result of crystal orientation, fin patterning and gate stack, and VT tuning through work function (WF) engineering. Mixed-mode simulations featuring quantum-corrected hydrodynamic transport models are performed on large Monte Carlo ensembles. A conservative $mu- 6.40sigma$ criterion is adopted to systematically evaluate read and write stability of these cells at different supply voltages. Simulation results and comparison with published measurements on fabricated cells help with assessing variability issues for FinFET-based SRAMs operating at low VDD, thus providing design guidelines for future technology nodes