This paper describes a method to manufacture through wafer via holes with tapered walls for RF applications. The main purpose was the need to obtain via holes with tapered walls that allow depositing seed and barrier layers by Physical Vapor Deposition (PVD) to enable gold electroplating. Method consists in consecutively using of the two basic process types for DRIE technique: isotropic and anisotropic etchings. Thus via holes with 20μm and 100μm diameter having tapered walls with angles between 14° and 18° were manufactured. Thin metal layers were also deposited on the walls by e-beam technique
We report on a continuous plasma etching process using SF6/O2/Ar gases for fabricating 100 μm deep t...
The possibility of using through-mask electrodeposition to fill features with active sidewalls was i...
One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma ...
This paper describes a method to manufacture through wafer via holes with tapered walls for RF appli...
This paper reports a method on the manufacturing of through silicon wafer via holes with tapered wal...
This paper reports a method on the manufacturing of through wafer via holes in silicon with tapered ...
A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafe...
A new process for through-wafer interconnects was studied by our group. This new process was develo...
This paper presents for the first time influence of the silicon resistivity over the DRIE processes....
Through-wafer electrical connections are becoming increasingly important for Micro-Electro-Mechanica...
A new approach to etch structures with vertical sidewalls in Si is presented. This process reduces t...
Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave ...
A fast, reproducible, and reliable via hole dry etching process for GaAs monolithic microwave integr...
With the growing demands for transferring large amounts of data between components in a package, it ...
This article report a continuous plasma etching process using SF 6/O2/Ar gases for fabricating 100 µ...
We report on a continuous plasma etching process using SF6/O2/Ar gases for fabricating 100 μm deep t...
The possibility of using through-mask electrodeposition to fill features with active sidewalls was i...
One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma ...
This paper describes a method to manufacture through wafer via holes with tapered walls for RF appli...
This paper reports a method on the manufacturing of through silicon wafer via holes with tapered wal...
This paper reports a method on the manufacturing of through wafer via holes in silicon with tapered ...
A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafe...
A new process for through-wafer interconnects was studied by our group. This new process was develo...
This paper presents for the first time influence of the silicon resistivity over the DRIE processes....
Through-wafer electrical connections are becoming increasingly important for Micro-Electro-Mechanica...
A new approach to etch structures with vertical sidewalls in Si is presented. This process reduces t...
Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave ...
A fast, reproducible, and reliable via hole dry etching process for GaAs monolithic microwave integr...
With the growing demands for transferring large amounts of data between components in a package, it ...
This article report a continuous plasma etching process using SF 6/O2/Ar gases for fabricating 100 µ...
We report on a continuous plasma etching process using SF6/O2/Ar gases for fabricating 100 μm deep t...
The possibility of using through-mask electrodeposition to fill features with active sidewalls was i...
One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma ...