A new process for through-wafer interconnects was studied by our group. This new process was developed to facilitate metallised through wafer via holes manufacturing. V-shape profile can contribute to an easier metallisation process and better adhesion. Manufacturing process use the possibility to change the isotropy in the Deep Reactive Ion Etching (DRIE) equipments from anisotropic to completely isotropic. Two slightly different processes were used in order optimize the technology and to see the changes introduced by isotropic/anisotropic processes sequence
The key enabling technology for 2.5D and 3D packaging applications is the through silicon via (TSV),...
A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafe...
This paper presents the experimental investigation of stepped deep reactive ion etching (DRIE) proce...
This paper reports a method on the manufacturing of through wafer via holes in silicon with tapered ...
This paper reports a method on the manufacturing of through silicon wafer via holes with tapered wal...
This paper describes a method to manufacture through wafer via holes with tapered walls for RF appli...
This paper presents for the first time influence of the silicon resistivity over the DRIE processes....
Through-wafer electrical connections are becoming increasingly important for Micro-Electro-Mechanica...
Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of...
TSV has emerged as a promising technique for three dimensional packaging. Square TSV is employed for...
A new approach to etch structures with vertical sidewalls in Si is presented. This process reduces t...
In this paper, we report on results of an intensive study, which has been performed to understand an...
We present 3 different types of interconnection vias fabricated by deep reactive ion etching (DRIE) ...
The Deep Reactive Ion Etching (DRIE) technology is widely used to fabricate high aspect ratio struct...
The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. T...
The key enabling technology for 2.5D and 3D packaging applications is the through silicon via (TSV),...
A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafe...
This paper presents the experimental investigation of stepped deep reactive ion etching (DRIE) proce...
This paper reports a method on the manufacturing of through wafer via holes in silicon with tapered ...
This paper reports a method on the manufacturing of through silicon wafer via holes with tapered wal...
This paper describes a method to manufacture through wafer via holes with tapered walls for RF appli...
This paper presents for the first time influence of the silicon resistivity over the DRIE processes....
Through-wafer electrical connections are becoming increasingly important for Micro-Electro-Mechanica...
Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of...
TSV has emerged as a promising technique for three dimensional packaging. Square TSV is employed for...
A new approach to etch structures with vertical sidewalls in Si is presented. This process reduces t...
In this paper, we report on results of an intensive study, which has been performed to understand an...
We present 3 different types of interconnection vias fabricated by deep reactive ion etching (DRIE) ...
The Deep Reactive Ion Etching (DRIE) technology is widely used to fabricate high aspect ratio struct...
The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. T...
The key enabling technology for 2.5D and 3D packaging applications is the through silicon via (TSV),...
A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafe...
This paper presents the experimental investigation of stepped deep reactive ion etching (DRIE) proce...