Intrinsic Gettering in a CCD/CMOS Process

The intrinsic gettering effect on our CCD/CMOS process has been evaluated by processing silicon wafers having 13.2 and 17.5 ppm of interstitial oxygen concentration, [Oi]. Electrical characterization in terms of both effective carrier generation lifetime in MOS structures and leakage current density of diodes, have shown a better electrical performances for sample having lower [Oi]. This has been related to the absence of surface stacking faults as verified after etching with Wright solution