Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis

As the size of transistor is shrinking, the difficulty of a design to meet timing has increased. Also, continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification (PV) process or Static Timing Analysis (STA) tool is unable to cover the timing verification of asynchronous based design, asynchronous design is changed to synchronous based for the STA tools to ensure the silicon timing can be met across various PVT. Synchronous design is a design where the transaction of data is governed by clock whereas asynchronous is a design where the transaction of data is event based which is not based on clock. Intel 8254 Programmable Interval Timer (PIT) which is an asynchronous based design is used as a case study in this research. A design flow which included the asynchronous path identification and technique implementation from asynchronous to synchronous without functionality changes has been proposed. Techniques conversion from asynchronous to synchronous including the clock placement, delays, combinational loop, latch, clock domain crossing, and reset are implemented on the 8254 PIT. The functionality of the synchronous 8254 PIT is validated with total of 22 test cases. Result shows the timing analysis coverage of 8254 PIT by STA has been increased from 40% in asynchronous design based to 91% in synchronous design based. The timing analysis coverage of new synchronous 8254 PIT will be 100% if excluding the asynchronous reset path